Full Channel-Swap Crossbar

ABSTRACT

A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an Ethernet physical layer device (PHY) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first, input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate. The crossbar switch can be used for Ethernet communications with various communication speeds, such as 10BaseT, 100BaseT, and Gigabit communications. A crossbar switch can be used in both a transmit path and a receive path. Two crossbar switches may be used in a receive path in order to undo channel swapping for control signal processing. A method of channel-swapping in an Ethernet PHY communications system is also presented.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 11/819,744, filed on Jun. 28, 2007, which claims the benefit ofU.S. Provisional Patent Appl. No. 60/905,815, filed on Mar. 9, 2007;U.S. patent application Ser. No. 11/819,744 is also acontinuation-in-part of U.S. patent application Ser. Nos. 10/612,729 and10/612,025, both filed on Jul. 2, 2003, all of which are incorporated byreference herein in their entireties.

BACKGROUND OF THE INVENT ON

1. Field of the Invention

The present invention generally relates to Ethernet physical layerdevice (PHY) communications systems, and more specifically to channeldesignation within such a system.

2. Related Art

A conventional Ethernet communications system includes an Ethernet PHYdevice having a transceiver that can transmit signals or data over awire or cable to another Ethernet PHY device that receives thetransmitted signals or data. The transmitting PHY typically, converts adigital, signal to an, analog signal (e.g., using a digital-to-analogconverter (DAC)) prior to providing the signal to the cable. Thereceiving PHY typically converts the received analog signal back to adigital signal (e.g., using an analog-to-digital converter). The cableis typically an unshielded twisted-pair cable (usually copper) thattypically contains four twisted pairs within its sheath. The PHYs andcable are capable of transmitting and receiving the signals or data at awide range of different speeds, including the typical 10BaseT, 100BaseT,and 1000BaseT (Gigabit) speeds.

The twisted pairs of a cable correspond to channels. Therefore, in acable with four twisted pairs, there are four channels. In both 10BaseTand 100BaseT communications, transmission is done on one twisted pair(i.e., a first channel), and reception is done on another twisted pair(i.e., a second channel), leaving two channels unused. With Gigabitcommunications, however, there is simultaneous bidirectionaltransmission over all four channels. Therefore, with Gigabitcommunications, channel ordering is extremely important. Anymisinterpretation of the channel order can cause a failure in link.

However, various problems can occur that will impede or prevent theproper functioning of a conventional Ethernet communications system asjust described. These problems include a variety of cable impairments,board-level miswiring, or even intentional design practices. One exampleis that a wile inside the cable could be broken, leaving no connectionon that twisted pair between a transmitting PHY and a receiving PHY onthe other side. As a second example, the wiring inside of the cablecould be incorrect. For instance, channel 1 of a transmitting PHY isexpected to be connected to channel 1 of a receiving PHY, but is insteadconnected to channel 2. As a third example, a customer's or user'sexpectations with regard to chip pinout or connector placement for eachchannel, could be erroneous, possibly making it necessary to rewire theuser's board, which can be costly.

The consequences of miscoupling PHY interfaces in a communicationssystem could result in an inoperable system, system failure, ormalfunctioning or damaged equipment. In an effort to prevent or mitigatethe effects of these occurrences, various solutions have beenimplemented. These solutions include automatic media dependent interface(MDI) crossover (auto-MDIX), Ethernet@wirespeed, and cable diagnostics.

Auto-MDIX can be used in a typical four-pair system to detect andreconfigure the order of either pairs 1 and 2 or pairs 3 and 4.Auto-MDIX can be useful in eliminating the need for crossover cablesthat may be utilized between two computers, for example. A drawback ofauto-MDIX, however, is that since auto-MDIX is limited to reconfiguringonly pairs 1 and 2 or pairs 3 and 4, it cannot handle other wiringconfiguration combinations. For example, auto-MDIX would not be able tocorrect coupling involving pairs 1 and 3, 1 and 4, 2 and 3, or 2 and 4.Auto-MDIX is also not useful when one of the two main cable pairs isphysically impaired (e.g., by a short or open circuit). Auto-MDIX isused throughout the industry, but may have other various names.

Ethernet@wirespeed provides an algorithm that can detect conditions on acable or at a PHY, and can alter a transmission that cannot be supportedunder the detected conditions. For example, Ethernet@wirespeed canautomatically reduce a transmission speed (e.g., from 1000BaseT to10/100BaseT) when optimal transmission cannot be maintained due todetected channel impairments. Ethernet wirespeed is useful when channelcharacteristics have degraded but the channel is still required forproviding communication. Drawbacks of Ethernet@wirespeed are that itcannot operate on a broken or damaged twisted pair, and it does not havethe capability to reconfigure wire pairs in order to utilize other goodpairs within the cable. For example, even though pair 3 or pair 4 may beunused, if pair 1 or pair 2 is damaged or broken, Ethernet@wirespeeddoes not have the capability to reconfigure pair 3 or pair 4 forcommunication.

Cable diagnostics can provide information pertaining to thecharacteristics and quality of a cable. For example, cable diagnosticscan detect an open, short, or proper termination on the cable. Inaddition, cable diagnostics can determine the cable length and canprovide information regarding the location of an impedance mismatch inthe cable. However, cable diagnostics do not have the capability todetermine whether the cable has been incorrectly installed. For example,cable diagnostics will not be able to detect or report that pair 1 hasbeen swapped with pair 3. Thus, cable diagnostics everything may reportthat satisfactory, even if pair 1 has been swapped with pair 3.

What is needed are Ethernet PHY communications system implementationsthat allow for correction of the miscoupling and/or misconfiguration ofEthernet PHY interfaces while overcoming the limitations of previoussolutions.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings illustrate the present invention and, togetherwith the description, further serve to explain the principles of theinvention and to enable one skilled in the pertinent art to make and usethe invention.

FIGS. 1-3 are block diagrams of conventional Ethernet physical layerdevice (PHY) communications system architectures.

FIG. 4 is a simplified diagram illustrating signal processing channelsof a conventional PHY and cable.

FIGS. 5A-5G illustrate various problem conditions of a cable or chipthat would benefit from the present invention.

FIG. 6 illustrates a channel-swap crossbar in a PHY, according to anembodiment of the present invention.

FIG. 7 illustrates channel designation mapping and use of a channel-swapcrossbar, according to an embodiment of the present invention.

FIG. 8 illustrates channel designation mapping and use of a channel-swapcrossbar for 10BaseT or 100BaseT communications, according to anembodiment of the present invention.

FIG. 9 illustrates a channel designation mapping and programmingexample, according to an embodiment of the present invention.

FIG. 10 illustrates a full swap transmit example circuit at asingle-channel level, according to an embodiment of the presentinvention.

FIG. 11 illustrates a full swap receive example circuit at asingle-channel level, according to an embodiment of the presentinvention.

FIG. 12 illustrates a Gigabit transmit path circuit, according to anembodiment of the present invention.

FIG. 13 illustrates a Gigabit receive path circuit for a particularsingle channel, according to an embodiment of the present invention.

FIG. 14 illustrates a clock recovery loop, according to an embodiment ofthe present invention.

FIG. 15 illustrates a programmable gain amplifier (PGA) control loop,according to an embodiment of the present invention.

FIG. 16 is a flowchart that illustrates a method 1600 ofchannel-swapping in an Ethernet PHY communications system, according toan embodiment of the present invention.

FIG. 17 is a flowchart illustrating step 1604 of method 1600, accordingto an embodiment of the present invention.

FIGS. 18 and 19 are flowcharts that each illustrate a further step ofmethod 1600, with regard to receiving signals at a PHY from an actualchannel, according to an embodiment of the present invention.

FIG. 20 is a flowchart illustrating step 1902, with regard to unswappingchannels in order to process control signals, according to an embodimentof the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following describes a full channel-swap crossbar for use in anEthernet PHY communications system that provides a way to easily connectfor miscoupling and/or misconfiguration of Ethernet PHY interfaces.

U.S. patent application Ser. No. 10/612,025 (entitled, “Method AndSystem For Secure Automatic Media Dependent Interface ReconfigurationAnd Repair”) and Ser. No. 10/612,729 (entitled, “Method And System ForAutomatic Media Dependent Interface Reconfiguration And Repair”), bothfiled Jul. 2, 2003, provide general solutions to the problem of how toallow a single Ethernet PHY to be as configurable as possible withrespect to the media channels on which it operates. U.S. patentapplication Ser. Nos. 10/612,729 and 10/612,025 are incorporated byreference herein in their entireties. The following description provideshardware implementation embodiments that complement the generalsolutions of these incorporated applications.

FIG. 1 illustrates a conventional Ethernet PHY communications system100, with a first PHY device 102 connected to a second PHY device 104 bycommunication links 106/108. System 100 can be used to transmitcommunications such as data and power. The first PHY device 102 includesa transceiver 110, and also includes transformers 116 and 118 thatprovide for transport of communication signals between communicationlinks 106/108 and transceiver 110. The second PHY device 104 likewiseincludes a transceiver 120, and also includes transformers 126 and 128that provide for transport of communication signals betweencommunication links 106/108 and transceiver 120. Transformers 116, 118,126, and 128 are passive electrical components (magnetics modules) thatconvert electrical signals from one level to another as well as provideelectrical isolation of the cable from the chip. Each PHY device 102/104typically includes one or more DACs (not shown) to convert digitalsignals to analog signals prior to transmitting on communication links106/108. Likewise, each PHY device 102/104 typically includes one ormore ADCs (not shown) to convert analog signals to digital signals oncethe signals are received from communication links 106/108. Communicationlinks 106/108 can each represent, for example, a twisted pair of anunshielded twisted-pair cable 105, such as a CAT-5 cable using a 10,100, or 1000BaseT Fast Ethernet standard.

As it appears in FIG. 1, communication link 106 represents a firstchannel connecting a first channel port 112 of the first PHY 102 to afirst channel port 122 of the second PHY 104. Likewise, it, appears thatcommunication link 108 represents a second channel connecting a secondchannel port 114 of the first PHY 102 to a second channel port 124 ofthe second PHY 104. However, it could, instead, be that communicationlink 106 connects the first channel port 112 to the second channel port124, and that communication link 108 connects the second channel port114 to the first channel port 122 (see Ethernet PHY communicationssystem 200 of FIG. 2). This could be the case, for example, if the cablerepresented by communication links 106/108 is actually a crossovercable. For example, transmission from the first PHY 102 to the secondPHY 104 can be accomplished from a first channel port e.g. channel port112) over wire 230 to a second channel port (e.g. channel port 124).Likewise, in the crossover cable example, transmission from the secondPHY 104 to the first PHY 102 can be accomplished from a first channelport (e.g., channel port 122) over wire 232 to a second channel port(e.g., channel port 114).

FIGS. 1 and 2, only two twisted pairs (two channels) are shown forsimplicity. In a typical four-wire (four twisted-pair) cable, for10BaseT or 100BaseT, only two of the twisted pairs are in fact used. Foreach PHY device, one pair would be used for transmitting, and one pairfor receiving. The other two twisted pairs would go unused. For Gigabitcommunications, however, all four twisted pairs would be used forsimultaneous transmitting and receiving. A typical four-wire cable isshown in system 300 of FIG. 3, As can be seen, system 300 is similar tosystem 100, with the addition of transformers 117 and 119 as channelports 113 and 115 of transceiver 110, transformers 127 and 129 aschannel ports 123 and 125 of transceiver 120, and correspondingcommunication links 107 and 109.

FIG. 4 is a simplified diagram 400 showing signal processing channels ofa conventional PHY 402 and cable 405. For simplicity, only signaltransmission is shown, PHY 402 has four channel ports: 0, 1, 2, and 3.From channel port 0, a digital signal 434 is converted to an analogsignal 438 via DAC 436 prior to transmission over twisted pair 440 ofcable 405. Twisted pair 440 is shown in FIG. 4 as if it were a part of acrossover cable. However, it could also be a twisted pair of a straightcable, such as twisted pair 442. Both crossover and straight pairs areshown in FIG. 4 for example only. It is unlikely that both would be usedin the same cable. When receiving a signal from cable 405, an analogsignal would be converted to a digital signal via an ADC (not shown)within PHY 402.

As described above in the Background section of this document, variousproblems can occur that will impede or prevent the proper functioning ofa conventional Ethernet communications system as just described, whichcould result in an inoperable system, system failure, or malfunctioningor damaged equipment. The various problems include a variety of cableimpairments, board-level miswiring, or even intentional designpractices. Examples of these problems are shown in FIG. 5.

In FIGS. 5A-5C, a first PHY 502 is connected to a second PHY 504, viacable 505. In FIG. 5A, channel ports 1 and 2 are swapped at second PHY504 (see the channel ports referenced by 544). This could result, forexample, in unexpected signals received at channel ports 1 and 2 of PHY504. In FIG. 5B, twisted pairs 546 and 548 are crossed, such thatchannel port 0 of PHY 502 is connected to channel port 2 of PHY 504instead of channel port 0 of PHY 504. Similarly, channel port 2 of PHY502 is connected to channel port 0 of PHY 504 instead of channel port 2of PHY 504. This crossing is an indication of a possible miswiringwithin cable 505. This could again result unexpected signals received.In FIG. 5C, twisted pair 550 is broken, therefore providing noconnection between channel port 1 of PHY 502 and channel port 1 of PHY504.

FIGS. 5D-5G show example chip pinout/connector configurations in which aparticular configuration might be different than a user's expectations.This can occur, for example, because transformer formats differ in theirconnector configurations. For example, in a single-port design such asthat shown in FIG. 5D, the channel ordering 552 at the pinout of a PHYchip 553 may be opposite of the channel ordering 554 of the pinout of amagnetics module 555.

FIG. 5E shows a side view of a multiple-port Ethernet implementationinvolving a multiple-port PHY chip and an RJ45 connector. An RJ45connector is typically a plastic cable connector that is used to connectUTP Ethernet cables. Each RJ45 socket represents one Ethernet port. InFIG. 5E, a side view of a multiple-port PHY chip 556 is shown withport/channel ordering 557 having ports D, C, B, and A in a single row. Aside view of an RJ45 connector 558 is shown with port/channel ordering559 where ports D, C, B, and A are stacked in two rows of twoconnectors. The channel ordering within each RJ45 socket is determinedby the manufacturer of the connector module and might not correspondwith the channel ordering at the pinout of the fixed channel ordermultiple-port PHY chip. As shown in FIG. 5E, there are channel ordermismatches on ports B and D that would necessitate board wiring that mayrequire eight sensitive signals, for example (i.e., one for eachmismatched channel), to completely cross over each other. This is bothdifficult to achieve and potentially damaging to signal quality.

In the top-view example, shown in FIG. 5F, single-port channel ordering560 of the pinout configuration of PHY chip 561 does not align withchannel ordering 562 of RJ45 connector (or magnetics module) 563.Similarly, in a multiple-port implementation such as that shown in thetop-view example of FIG. 5G, channel ordering 564 of port A of PHY chip565 aligns with channel ordering 566 of port A of RJ45 connector (ormagnetics module) 567. However, channel ordering 568 of port B of PHYchip 565 does not align with channel ordering 569 of port B of RJ45connector (or magnetics module) 567. In all of these examples, differinguser expectations can result in an inoperable or failing system.

One solution that can be used to avoid or correct potential problems,such as those described above, is to provide a switching mechanism toremap a virtual channel designation to an actual channel designation.This can be done with a channel-swap crossbar switch, as will now bedescribed. FIG. 6 is a simplified diagram 600 showing signal processingchannels of a PHY 602 and cable 605. In an embodiment of the presentinvention, PHY 602 includes a channel-swap crossbar switch 670 thatoperates on one or more digital signals. This occurs in the digitalportion of PHY 602. For each channel port of PHY 602, the channel-swapcrossbar switch includes at least one multiplexer 672 for selecting areceived signal for that particular channel port. In the receivedirection of data flow, the channel-swap crossbar switch operates onsampled data words produced by the ADC (not shown) of each channel.Likewise, for each channel port of PHY 602, the channel-swap crossbarswitch includes at least one multiplexer 674 for designating an actualchannel on which to transmit a particular input signal. In the transmitdirection, the channel-swap crossbar switch operates on the symbolstreams heading toward the DAC (not shown) of each channel. In anembodiment, each multiplexer receives all of the input signals andselects which one to designate to a particular channel. The change froman input signal's original, or virtual, channel designation to its newactual channel designation is considered a “channel-swap”. This“channel-swap” is described further with reference to FIG. 7.

FIG. 7 shows an example mapping 772 of virtual digital channels 774mapped to actual analog channels 776. In this example, virtual digitalchannel 0 is mapped to actual analog channel 1, virtual digital channel1 is mapped to actual analog channel 3, virtual digital channel 2 ismapped to actual analog channel 0, and virtual digital channel 3 ismapped to actual analog channel 2. This mapping is also shown by linesdrawn in PHY 602. This means, for example, that a digital signal comingin at virtual digital channel 2 will be transmitted as an analog signalon actual channel 0 of cable 605, as shown by the example 773, whichshows, for example, the first multiplexer 674 (shown in FIG. 6).

Since the example shown in FIG. 7 uses all four channels, it is notappropriate for 10BaseT or 100BaseT communications, which only use twochannels. However, one advantage of the present invention is that10BaseT and 100BaseT communications can be transmitted over any twocable pairs (channels), not only the main two pairs. An example of thisis shown in FIG. 8, where only two channels are mapped in mapping 872.

The mappings 772/872 shown in FIGS. 7 and 8 can be programmed. Forexample, the mapping can be controlled by setting on-chip registers.Alternatively, this can be done using chip inputs. An example registerbit configuration 978 for mapping channels using the channel-swapcrossbar switch is shown in FIG. 9, according to an embodiment of thepresent invention. As can be seen in the register bit configuration 978,there are four channel selection fields and each channel selectdesignation is two bits. This would be required for a four-channelsystem, where the four channels 0, 1, 2, and 3 would be designated bybit combinations 00, 01, 10, and 11, respectively. Although a typicalEthernet communications system has four channels, the invention is notto be limited to this. The invention can be easily adapted to handle anynumber of channels, as would be understood by those skilled in therelevant art(s).

In FIG. 9, mapping example 980 shows the bits to set for a particularmapping. In example 980, in order to map digital (virtual) channel 0 toanalog (actual) channel 3, the channel 0 select field is set to 11. Tomap digital channel 1 to analog channel 0, the channel 1 select field isset to 00. To map digital channel 2 to analog, channel 1, the channel 2select field is set to 01. Finally, to map digital channel 3 to analogchannel 2, the channel 3 select field is set to 10. In the examplesshown, the mapping assigns an analog channel to each digital channel.However, the invention is not to be limited to this. It would beunderstood by those skilled in the relevant art(s) that the mappingcould be done in the opposite way (i.e., a digital channel could beassigned to each analog channel).

Problems can occur if a channel is overmapped. In FIG. 9, mappingexample 982 shows analog channel 0 as being overmapped. In example 982,analog channel 0 is mapped to digital channels 0, 1, and 2. Whentransmitting, signals coming in on digital channels 0, 1, and 2 will alltry to transmit over actual channel 0. When receiving, signals coming infrom analog channels 2 and 3 will be ignored. This is a programmingerror. Effects of this programming error can be prevented by providinglogic to detect when overmapping has occurred. The programming erroritself can also be prevented by implementing logic that makes itimpossible for programming a mapping incorrectly in the first place.However, the details surrounding coding and/or implementation of thesetypes of detection and preventative logic will not be discussed here.

FIG. 10 illustrates a full swap transmit example circuit 1084 at asingle-channel level, according to an embodiment of the presentinvention. The multiplexer 1074 can represent one of the multiplexers674 from FIG. 6, for example. The priority encoding chart 1086 can beused to prioritize the channel mapping in case of overmapping, discussedearlier. In addition, when receiving a signal, a mapping itself (e.g., amapping defined in a register) is not enough. For example, in a mappingof digital channel 2 to analog channel 1, the channel 2 select field isset to 01 for signal transmission. The setting of bits 01 is equal tothe value of 1, which is the analog channel number desired. However whena signal is received and needs to map the analog channel to a digitalchannel, the system will not know that the “channel 2 select field” ofthe register represents digital channel 2 without further logic. Thepriority encoding chart 1086 can be used to address this. A kill valueis available if a channel is not to be assigned.

FIG. 11 illustrates a full swap receive example circuit 1188 at asingle-channel level, according to an embodiment of the presentinvention. The multiplexer 1172 can represent one of the multiplexers672 from FIG. 6, for example.

FIG. 12 illustrates a transmit path circuit 1290 used for Gigabitcommunications, according to an embodiment of the present invention.Transmit path circuit 1290 includes channel-swap crossbar switch 1270.Channel-swap crossbar switch 1270 can represent a transmit portion ofchannel-swap crossbar switch 670 of FIG. 6, for example.

FIG. 13 illustrates a receive path circuit 1392 used for Gigabitcommunications for a particular single channel, according to anembodiment of the present invention. Receive path circuit 1392 includesmultiplexer 1372. Multiplexer 1372 can represent a multiplexer 672 of achannel-swap crossbar switch 670 (shown in FIG. 6), for example.

Receive circuits require more complexity than transmit circuits. Thetransmit symbols that enter a DAC prior to transmission are small—two orthree bits, depending on the speed of operation. However, the receivesymbols that exit an ADC can be much larger (e.g., 8-bit words orgreater), and these received symbols contain a lot of noise, which needsto be lessened or removed. Therefore, further logic is needed whenreceiving signals to handle further control signal processing needs.Control signal processing, as used in this document, refers to digitalsignal processing techniques that are used to control many properties ofsignal recovery algorithms. Examples of control signal processinginclude automated gain control (AGC) loops for programmable gainamplifiers (PGA), clock phase recovery loops, and the like.

One such logic circuit for handling further control signal processing isthe clock recovery loop circuit 1494 shown in FIG. 14. After analogsignals are received at analog front end (AFE) 1495, they are convertedto digital signals using ADCs 1496. The resulting digital words could belarge (e.g., 8-hit words). The digital words then enter digital signalprocessing block 1497. For each channel, each digital word enters itsown receive path circuit 1492, where channel swapping occurs at its ownmultiplexer 1472 and noise introduced by the analog channel is removed.In further processing, a phase control word is selected for timingpurposes. However, phase control is an analog control, so the phasecontrol word is mapped back to the analog domain using channel-swapcrossbar 1498.

Another such logic circuit for handling further control signalprocessing is the programmable gain amplifier control loop circuit 1599shown in FIG. 15. After analog signals are received at analog front end(AFE) 1595, they are converted to digital signals using ADCs 1596.Again, the resulting digital words could be large (e.g., 8-bit words).The digital words then enter digital signal processing block 1597. Foreach channel, each digital word enters its own receive path circuit1592, where channel swapping occurs at its own multiplexer 1572 andnoise introduced by the analog channel is removed. In furtherprocessing, an automated gain control (AGC) control word is selected forattenuation control. The AGC control word tells AFE 1595 how much toattenuate the signal that's coming in. If the signal is very large, ittells it to attenuate it a lot in order to make it as small as possibleso that it does not overwhelm digital processing block 1597. However,attenuation control is an analog control, so the AGC control word ismapped back to the analog domain using channel-swap crossbar 1598.

As stated earlier, the present invention can be useful in avoiding orcorrecting potential problems including misconfiguration of channelports, miswiring of a board or cable, faulty or broken wires in a cable,and user expectation. However, there are many other potential uses forthe channel-swap cross-bar switch. For example, for data securitypurposes, data can be rerouted onto another channel so that sensitivedata does not flow on an expected channel. A further example is timedomain reflectometry (TDR). Time domain reflectometry is a way tocharacterize a communications system and detect possible problems in thesystem or cable. In general terms, with time domain reflectometry, asignal is driven on one channel, and its reflection, or return signal,is expected on the same or another channel. In the detected reflectionor return signal a variety of properties and characteristics can bedetermined. For example, the cable length, a break in the cable, orproper cable termination can be determined. In addition, crosstalk—aproperty of transmission data on one wire affecting a near wire to somedegree—can be determined. A benefit of using the present invention withtime domain reflectometry is that the channel(s) used for transmissionand the channel(s) used for detection can be very well controlled.

FIG. 16 is a flowchart describing a method 1600 of channel-swapping inan Ethernet PHY communications system, according to an embodiment of thepresent invention. Method 1600 starts at step 1602, In step 1604, achannel-swap crossbar switch is programmed to associate incoming channeldesignations with outgoing channel designations. In an embodiment, thechannel-swap crossbar switch consists of multiplexers such that eachmultiplexer is associated with an outgoing channel designation, asdescribed above with reference to FIGS. 6-11. The programming of thechannel-swap crossbar switch of step 1604 can be done by programmingeach multiplexer to associate one of the incoming channel designationsto the multiplexer's outgoing channel designation, as shown in FIG. 17(step 1702). This programming can be done by setting register bits orsetting chip inputs (e.g., pins), for example. In step 1606, two or moreinput signals are received, each input signal having an incoming channeldesignation. For each channel, one of the received input signals isselected to be provided to the channel based on its incoming channeldesignation in step 1608. Method 1600 ends at step 1610.

According to method 1600, a first input signal associated with aparticular channel cart be swapped to another channel as operatingconditions necessitate. As discussed above, these operating conditionscan include maintaining a specific channel order, inconsistent connectortypes, a broken wire or an incorrectly built cable, differences intransformer formats, etc. When any of these types of conditions aredetected or known, method 1600 can be used to work around them byrerouting transmissions onto other channels. Method 1600 can also beused intentionally, rather than to correct or avoid a problem. Forexample, method 1600 can be used to protect a sensitive datatransmission by changing its routing to an unexpected channel. Inaddition, method 1600 can be used for controlling the channels used fortime domain reflectometry.

FIG. 18 is a flowchart 1800 that illustrates a further step of method1600, with regard to receiving signals from an actual channel, accordingto an embodiment of the present invention. After two or more inputsignals are received in step 1606 as “received” signals from an actual(analog) channel, the signals are processed in step 1802 to remove noisethat may have been introduced by their associated actual channels. Thiscan occur after step 1606 or 1608. The method then returns to step 1608or 1610 of method 1600.

FIG. 19 is a flowchart 1900 that illustrates another further step ofmethod 1600, with regard to receiving signals from an actual channel,according to an embodiment of the present invention. After two or moreinput signals are received in step 1606 as “received” signals from anactual (analog) channel, and after any channel-swapping (to the digitaldomain) is done in step 1608, channel-swapping of step 1608 is undone instep 1902 in order to provide control signal processing. The method thencontinues at step 1610. This ‘unswapping’ is done when certain controlsignal processing needs to be done in the analog domain. Examples ofcontrol signal processing needs that require this are clock recovery andPGA control. An example of this ‘unswapping’ is illustrated in FIG. 20.

FIG. 20 is a flowchart illustrating step 1902, with regard to unswappingchannels in order to process control signals, according to an embodimentof the present invention. In step 2002, another channel-swap crossbarswitch is programmed to associate incoming channel designations withoutgoing channel designations. In step 2004, two or more previouslyswapped receive input signals are received, each previously swappedreceive input signal having an incoming channel designation. The term“previously swapped” is not meant to imply that a particular receivesignal was actually swapped by the initial channel-swap cross-barswitch. Rather, what is meant is that it was previously processed by theinitial channel-swap crossbar switch, whether or not any channelswapping actually occurred. For each channel, one of the previouslyswapped received input signals is selected to be provided to the channelbased on its incoming channel designation in step 2006. The method thenreturns to step 1610.

The present invention has been described as operating on digital signalswithin the digital portion of a PHY device. However, the invention isnot to be limited to digital implementations, nor is the invention to belimited to being necessarily located within a PHY device. While thechannel-swap crossbar function can be implemented in either the analogor digital domains, a digital implementation has the followingadvantages. First, digital pathways are more robust. Digital circuitryis much less sensitive to process and temperature. Any additionalloading of switches needed to perform the channel-swap crossbar onanalog pathways would make the implementation of the DAC and ADC morechallenging. Second, there is minimal impact on silicon area and powerconsumption with a digital implementation. As the transistor featuresize in the digital portion of a chip continues to drop, the analogportion tends to consume an ever larger percentage of the total space.An analog implementation of the channel-swap crossbar switch wouldlikely consume more silicon area than a corresponding digitalimplementation, and the disparity could grow even larger in futuregenerations. Third, a digital implementation is likely to be moreportable to future generations. In addition to the area and powersavings, digital implementations are inherently much easier to passalong from one generation of silicon to the next. Finally, becausetestability circuits were previously implemented in digital portions ofa chip, it would be easier to debug any problems with a digitalimplementation of the channel-swap crossbar switch than an analogimplementation.

A full channel-swap crossbar for use in Ethernet PHY communicationssystems has just been described. The channel-swap crossbar provides away to easily correct for miscoupling and/or misconfiguration ofEthernet PHY interfaces. Advantages of the channel-swap crossbar includeallowing full reconfiguration of cable pairs for Gigabit communications,where any physical (actual) channel can be mapped to any virtualchannel. Cable pair order can be reversed easily, which eases siliconlayout or board layout difficulties. In addition, it allows 10BaseT or100BaseT communications to operate on any two cable pairs, not only onthe main two cable pairs. Further, the channel-swap crossbar can be usedfor data security in that data can be transmitted on an unexpectedchannel, and it can be used to control the channels used for time domainreflectometry.

CONCLUSION

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample and not limitation. It will be apparent to one skilled in thepertinent art that various changes in form and detail can be madetherein without departing from the spirit and scope of the invention.Therefore, the present invention should only be defined in accordancewith the following claims and their equivalents.

What is claimed is:
 1. A channel-swap crossbar switch, comprising: acontrol mechanism configured to effect a mapping of a virtual channel toan actual channel; a first multiplexer configured to select a signalreceived at a virtual channel port based on the mapping; and a secondmultiplexer configured to designate an actual channel on which totransmit the received signal based on the mapping.
 2. The channel-swapcrossbar switch of claim 1, wherein the control mechanism comprises chipinputs.
 3. The channel-swap crossbar switch of claim 1, wherein thecontrol mechanism comprises a register.
 4. The channel-swap crossbarswitch of claim 3, wherein the mapping comprises one or more bits storedin the register.
 5. The channel-swap crossbar switch of claim 1, furthercomprising logic configured to detect when an overmapping has occurred.6. The channel-swap crossbar switch of claim 5, wherein the logic isfurther configured to prioritize the channel mapping when theovermapping is detected.
 7. The channel-swap crossbar switch of claim 1,wherein the signal comprises a 10BaseT communication or a 100BaseTcommunication.
 8. The channel-swap crossbar switch of claim 1, whereinthe first multiplexer is configured to select the signal received at thevirtual channel port from among a plurality of signals received at aplurality of virtual channel ports.
 9. The channel-swap crossbar switchof claim 1, wherein the second multiplexer is configured to designatethe actual channel on which to transmit the received signal from among aplurality of actual channels.
 10. The channel-swap crossbar switch ofclaim 1, wherein the virtual channel port comprises a digital channelport.
 11. A method, comprising: receiving a mapping of a virtual channelto an actual channel; selecting a signal received at a virtual channelport based on the mapping; and designating an actual channel on which totransmit the received signal based on the mapping.
 12. The method ofclaim 11, wherein the receiving comprises receiving mapping signals viachip inputs.
 13. The method of claim 11, wherein receiving the mappingcomprises storing the mapping in a register.
 14. The method of claim 13,wherein the mapping comprises one or more bits.
 15. The method of claim11, further comprising detecting when an overmapping has occurred. 16.The method of claim 15, further comprising prioritizing the channelmapping when the overmapping is detected.
 17. The method of claim 11,wherein the signal comprises a 10BaseT communication or a 100BaseTcommunication.
 18. The method of claim 11, wherein selecting the signalcomprises selecting the signal from among a plurality of signalsreceived at a plurality of virtual channel ports.
 19. The method ofclaim 11, wherein designating the actual channel comprises designatingthe actual channel on which to transmit the received signal from among aplurality of actual channels.
 20. The method of claim 1, wherein thevirtual channel port comprises a digital channel port.